/*
 * Copyright (c) 2022-2023 Termony Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 *    conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 *    of conditions and the following disclaimer in the documentation and/or other materials
 *    provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without specific prior written
 *    permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _LOS_ARCH_CPU_H
#define _LOS_ARCH_CPU_H

#include "los_config.h"
#include "los_compiler.h"

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */

#define __REG32(x)          (*((volatile UINT32 *)(x)))
#define __REG64(x)          (*((volatile UINT64 *)(x)))

#define __WFI()             __asm__ __volatile__("wfi" ::: "memory")
#define __ISB()             __asm__ __volatile__("isb" ::: "memory")
#define __DSB()             __asm__ __volatile__("dsb" ::: "memory")
#define __DMB()             __asm__ __volatile__("dmb" ::: "memory")

#define GET_ARM_SYS_REG(CR, Rt) \
                __asm__ __volatile__("mrc " CR : "=r"(Rt) :: "memory")
#define SET_ARM_SYS_REG(CR, Rt) \
                __asm__ __volatile__("mcr " CR :: "r"(Rt) : "memory")

#define GET_ARM_SYS_REG64(CR, Rt) \
                __asm__ __volatile__("mrrc " CR : "=r"(Rt) :: "memory")
#define SET_ARM_SYS_REG64(CR, Rt) \
                __asm__ __volatile__("mcrr " CR :: "r"(Rt) : "memory")


#define MPIDR               "p15, 0, %0, c0, c0, 5"

/* AArch32 System register interface to GICv3. */
#define ICC_IAR0            "p15, 0, %0, c12, c8, 0"
#define ICC_IAR1            "p15, 0, %0, c12, c12, 0"
#define ICC_EOIR0           "p15, 0, %0, c12, c8, 1"
#define ICC_EOIR1           "p15, 0, %0, c12, c12, 1"
#define ICC_HPPIR0          "p15, 0, %0, c12, c8, 2"
#define ICC_HPPIR1          "p15, 0, %0, c12, c12, 2"
#define ICC_BPR0            "p15, 0, %0, c12, c8, 3"
#define ICC_BPR1            "p15, 0, %0, c12, c12, 3"
#define ICC_DIR             "p15, 0, %0, c12, c11, 1"
#define ICC_PMR             "p15, 0, %0, c4, c6, 0"
#define ICC_RPR             "p15, 0, %0, c12, c11, 3"
#define ICC_CTLR            "p15, 0, %0, c12, c12, 4"
#define ICC_MCTLR           "p15, 6, %0, c12, c12, 4"
#define ICC_SRE             "p15, 0, %0, c12, c12, 5"
#define ICC_HSRE            "p15, 4, %0, c12, c9, 5"
#define ICC_MSRE            "p15, 6, %0, c12, c12, 5"
#define ICC_IGRPEN0         "p15, 0, %0, c12, c12, 6"
#define ICC_IGRPEN1         "p15, 0, %0, c12, c12, 7"
#define ICC_MGRPEN1         "p15, 6, %0, c12, c12, 7"

#define ICC_SGI1R           "p15, 0, %Q0, %R0, c12"

/* AArch32 System register interface to General Timer. */
#define CNTFRQ              "p15, 0, %0, c14, c0, 0"
#define CNTPCT              "p15, 0, %Q0, %R0, c14"
#define CNTP_CTL            "p15, 0, %0, c14, c2, 1"
#define CNTP_TVAL           "p15, 0, %0, c14, c2, 0"
#define CNTP_CVAL           "p15, 2, %Q0, %R0, c14"


UINT32 HalGetCpuId(VOID);
UINT32 HalGetAffinity(VOID);
UINT32 HalGetAffinityFromCpuId(UINT32 cpuId);

#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

#endif /* _LOS_ARCH_CPU_H */